library verilog;
use verilog.vl_types.all;
entity dbg_top is
    generic(
        Tp              : integer := 1
    );
    port(
        tms_pad_i       : in     vl_logic;
        tck_pad_i       : in     vl_logic;
        trst_pad_i      : in     vl_logic;
        tdi_pad_i       : in     vl_logic;
        tdo_pad_o       : out    vl_logic;
        tdo_padoen_o    : out    vl_logic;
        capture_dr_o    : out    vl_logic;
        shift_dr_o      : out    vl_logic;
        update_dr_o     : out    vl_logic;
        extest_selected_o: out    vl_logic;
        bs_chain_i      : in     vl_logic;
        bs_chain_o      : out    vl_logic;
        risc_clk_i      : in     vl_logic;
        risc_addr_o     : out    vl_logic_vector(31 downto 0);
        risc_data_i     : in     vl_logic_vector(31 downto 0);
        risc_data_o     : out    vl_logic_vector(31 downto 0);
        wp_i            : in     vl_logic_vector(10 downto 0);
        bp_i            : in     vl_logic;
        opselect_o      : out    vl_logic_vector(2 downto 0);
        lsstatus_i      : in     vl_logic_vector(3 downto 0);
        istatus_i       : in     vl_logic_vector(1 downto 0);
        risc_stall_o    : out    vl_logic;
        reset_o         : out    vl_logic;
        wb_rst_i        : in     vl_logic;
        wb_clk_i        : in     vl_logic;
        wb_adr_o        : out    vl_logic_vector(31 downto 0);
        wb_dat_o        : out    vl_logic_vector(31 downto 0);
        wb_dat_i        : in     vl_logic_vector(31 downto 0);
        wb_cyc_o        : out    vl_logic;
        wb_stb_o        : out    vl_logic;
        wb_sel_o        : out    vl_logic_vector(3 downto 0);
        wb_we_o         : out    vl_logic;
        wb_ack_i        : in     vl_logic;
        wb_cab_o        : out    vl_logic;
        wb_err_i        : in     vl_logic
    );
end dbg_top;
